Modern integrated circuit (IC) chips comprise a semiconductor substrate and a large number of active devices (e.g., transistors, gates) which are formed in the substrate and which are interconnected to one another with conductive traces (lines). The traces typically are formed either of metal or of polysilicon, and resemble a ribbon having a width dimension (W) and a thickness dimension (T). A large number of such conductive traces are typically present on a given IC chip, and are spaced a distance (S) from one another.
As a general proposition, the trend is towards forming features, including conductive traces (e.g., metal lines), which are smaller and smaller, permitting an increasing number of active devices to be interconnected in increasingly complex manners on semiconductor devices, thereby enabling enhanced functionality and increased operating speeds. In other words, reducing device dimensions allows higher density logic integration and faster speeds. This has been the primary motivation of plunging into sub-micron dimensions. The scaling trend towards smaller-and-smaller dimensions leads to smaller feature size, complex device physics, increase of chip size, increase in operating frequencies and increase in chip complexity. The physical parameters affected are decrease of gate and metal width, spacing and thickness, decrease of dielectric thickness and increase of interconnect length. The scaling impact on the electrical parameters is potentially an increase of total capacitance, with increasingly dominant coupling effects, increase of interconnect resistance and the inductance effects at chip level. Interconnect effects, mainly delay, starts playing the dominant role in deciding the performance of the circuit at small geometries, such as 0.35 .mu.m and below. By plotting wire-length distribution over feature size and die size, it is evident that signal delay is dominated by RC interconnect peaks as we go to lower feature size and higher die size.
Scaling is not done by the same factors for all the variables i.e. length, width, thickness of gate and metal layers, dielectric thickness and voltage are not scaled by the same factors. It can be shown that in some cases it is not allowed by available technology, for example, some dimensions are not practicable by current lithography, diffusion, etc. limitations and other cases it will not lead to high performance ICs.
The technology solutions available to solve this problem are:
1) Increase in the number of layers, which will result in shorter interconnects; PA1 2) Using higher conductivity materials like copper, since resistance is inversely proportional to conductivity; and PA1 3) Using materials with low dielectric constant like polyimide.
All the above solutions leads to higher cost for production (fab) and design.
Utilizing what is now considered to be "old" technologies, feature sizes limited to on the order of &gt;0.5 .mu.m resulted, and resemble a wide ribbon having a width dimension (W) which is substantially in excess of the thickness dimension (T) along the length of trace for older technologies. In other words, typically W&gt;&gt;T, or the cross-sectional area ratio W:T is &gt;&gt;1.
Newer technologies, facilitating smaller geometries (on the order of 0.35 .mu.m feature size), permit near one-to-one (1:1) ratio of width-to-thickness, or tall thin cross-sectional structures over the length of a conductive trace.